vu84vu wrote:
當初大盤是要買哪檔...(恕刪)
1970年代出現了第一檔指數基金，1990年代ETF開始問世，至於在台灣出現的年代更晚。
股齡較大的投資朋友當初是沒有選擇的，不過來者可追，現在已經有不錯的追蹤大盤績效的投資工具。
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ebola01 wrote:
討論交流園地【定存...(恕刪)
https://semiengineering.com/samsung-unveils-scaling-packaging-roadmaps/
Samsung Unveils Scaling, Packaging Roadmaps
Foundry unit rolls out ambitious plan down to 4nm, along with 18nm FD-SOI and advanced packaging developments.
May 24th, 2017 - By: Ed Sperling
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Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise.
The moves put Samsung Foundry in direct competition with Intel, GlobalFoundries and TSMC, as well as Outsourced Semiconductor Assembly and Test vendors, across a wide swath of markets ranging from mobile devices to IoT, MRAM and RF. Samsung also announced its plan to begin risk production for 8nm LPP this year, and to begin using EUV in its 7nm LPP process next year. EUV is expected to reduce the number of photomasks required at that node by about 20.
Exactly what these numbers mean, and how they compare to other foundries, isn’t entirely clear, and there is discussion throughout semiconductor manufacturing sector that one foundry’s numbers don’t match another’s. But what is clear is that Samsung is attempting to pick up business at every node and half-node, including 8nm, 7nm, 6nm, 5nm, and 4nm, and it plans to introduce an 18nm version of its FD-SOI technology in 2019.
“This is now an independent foundry,” said Kelvin Low, senior director of foundry marketing at Samsung Foundry. “We will still leverage Samsung R&D and memory and logic. And we will utilize the company’s advanced packaging and manufacturing capacity. But we are now an independent business organization.”
This result, in effect, is being able to utilize the deep-pocket R&D of an IDM with a thriving end-market business in everything from televisions to smart phones, while also being able to utilize capacity of a newly constructed 300mm fab equipped with the latest technology, including EUV systems. Low said that with EUV the company is turning out 1,200 wafers per day, and he expects that number to improve.
Samsung has been in production on 10nm since late last year. The company issued a press release in March to that effect, saying it has shipped more than 70,000 wafers of its first-generation Low Power Early (LPE), although it didn’t discuss any additional details.
Joanne Itow, director of manufacturing at Semico Research, noted that all of the major foundries are scrambling to find out which process technologies will work best for which applications. Because many of the hot growth markets—automotive, industrial and regular IoT, augmented/virtual reality and medical—require new technology, it’s uncertain which process will win.
“Everyone is trying to figure out which process is best for which product, so foundries are opening up all of these processes,” Itow said. “This is coming from a variety of inquiries. Not every one can be a winner. Eventually, this will filter down to a few technologies. But customers do want different options this year, and we’re seeing the same thing happening with TSMC. They need to roll out something new. This is becoming a pervasive electronics applications market, and there are so many different types of products that we are seeing different processes to accommodate them.”
For Samsung in particular, this is a signal that the company is now courting a broader base of customers, she said. “In the past Samsung was very selective because they wanted to make sure they were successful with their product launches. Now, the next step is to get a broader base and to expand its foundry revenues.”
Samsung’s announcement also included developments at 8nm and 6nm. Samsung did not elaborate. But Sam Wang, a research vice president at Gartner, said the 8nm is a competitive move. “From a time-to-market point of view, it is inevitable that Samsung must offer a relaxed 7nm technology, in response to TSMC’s aggressive 7nm DUV schedule before EUV becomes ready,” he said. “Customers could not fully rely on Samsung’s 7nm EUV-only schedule, which has uncertainty because of the the exact progress of ASML (on EUV). In a way, Samsung’s 8LPP node is a relaxed 7nm node, which should be equivalent to TSMC’s N7, and Samsung’s 7LPP should be equivalent to TSMC’s N7+.”
Samsung also announced plans to introduce its first gate-all-around FET at 4nm in 2020 using EUV. This is the first time a foundry has publicly discussed a timetable for delivering GAA FETs, but roadmaps exist within a number of companies for several more nodes. That includes EUV lithography, GAA FETs using vertical and horizontal nanowires, and nanosheet FETs.
Kinam Kim, president of Samsung’s Semiconductor Business, said during a presentation at a recent event sponsored by Imec, a Belgium R&D organization, that the company sees a path to logic transistor scaling down to 1.5nm.
Then, using a 2D material called molybdenum disulfide (MoS2), Samsung believes it could scale logic technology even further. Samsung and others are exploring so-called MoS2 FETs. “We believe around 1nm is possible,” Kim said. Still in the R&D stage, MoS2 is a family of transition metal dichalcogenide (TMD) materials. The TMDs have remarkable electronic, optical and mechanical properties.
Fig. 1: Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet. Source: IBM.
In addition, Samsung announced its second-generation FD-SOI at 18nm in 2019 using immersion lithography. The company has been adding RF and other IP capabilities to its 28nm FD-SOI technology. Going forward, it plans to add embedded MRAM to FD-SOI, and eventually into finFET processes, as well. The company also is looking at FD-SOI for the automotive industry because it has a superior soft-error rate over bulk CMOS, said Low.
How this fares in the market is not clear. “On FD-SOI, we now have Samsung 28, 18nm, and GlobalFoundries’ 28, 22, and 12nm,” said Gartner’s Wang. “Since Samsung’s 18nm is independently developed by itself, it remains to be seen how GlobalFoundries will response to this 18nm offering.”
Back in CMOS, it appears that 10nm will be a long-lived node for Samsung. “We expect 10nm will be a very usable, long-life node,” Low said. “But some customers require a new node every year. So 7nm will be finFET on CMOS. 6nm will be smart scaling for area and power. 5nm will be finFET on CMOS. After that, we will show a post-finFET device, using a gate-all-around multi-bridge channel finFET.”
Perhaps the biggest surprise is a shift in the company’s advanced packaging. Samsung had hinted last year that it was looking for an alternative to silicon interposers because they are too expensive. The company is relying on a redistribution-layer (RDL) interposer to bridge logic to high-bandwidth memory, sidestepping commercial interposer technology for its 2.5D technology, and adding the same technology into its fan-outs.
Fig. 2: RDL interposer. Source: Samsung
Intel has introduced its own low-cost Embedded Multi-die Interconnect Bridge (EMIB), which is a silicon bridge that runs through the package substrate.
—Mark LaPedus contributed to this report.
原來除了gate first,gate last,還有最新的gate all around
http://www.eettaiwan.com/news/article/20160913NT01-Chip-Process-War-Heats-Up
半導體製程技術競爭升溫
IBS指出，在14奈米節點，FD-SOI的晶圓成本比FinFET低16.8%
（來源：IBS）
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ebola01 wrote:
討論交流園地【定存...(恕刪)
https://technews.tw/2017/07/12/samsung-aims-to-surpass-tsmc-in-7nm-foundry-by-next-year/
三星矢言 7 奈米明年超車台積電，5、6 奈米蓄勢待發
三星晶圓代工自立門戶後信心大增，不僅看好明年營收將大幅成長，且在晶圓製造技術方面，也務求超越領頭羊台積電。
據 ZDNET.com 報導，三星晶圓代工行銷副總 Sanghyun Lee 宣稱，明年導入全版極紫外光（EUV）微影技術後，晶圓良率與價格將會優於台積電，營收表現也會超越競爭對手。
上述可知 EUV 已被三星視為技術超越台積電的利器。在 EUV 的加持下，三星計劃在 2018 下半年先行量產 7 奈米製程，6 奈米與 5 奈米製程隨後也將於 2019 年上陣，如此將可提供三星客戶更多選擇。
不過無論三星技術多麼高超，最終仍要以市佔論成敗，但在這方面，三星 2016 年晶圓代工市佔 7.9%，全球排第四，遙遙落後台積電的 50.6%。（日經新聞）
另外據三星預測，全球晶圓代工市場今年將創造 610 億美元的產值，較 2016 年成長 7.2%，明年更是上看 652 億美元。
（本文由 MoneyDJ新聞 授權轉載；首圖來源：Samsung）
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三星晶圓代工自立門戶後信心大增，不僅看好明年營收將大幅成長，且在晶圓製造技術方面，也務求超越領頭羊台積電。
據 ZDNET.com 報導，三星晶圓代工行銷副總 Sanghyun Lee 宣稱，明年導入全版極紫外光（EUV）微影技術後，晶圓良率與價格將會優於台積電，營收表現也會超越競爭對手。
上述可知 EUV 已被三星視為技術超越台積電的利器。在 EUV 的加持下，三星計劃在 2018 下半年先行量產 7 奈米製程，6 奈米與 5 奈米製程隨後也將於 2019 年上陣，如此將可提供三星客戶更多選擇。
不過無論三星技術多麼高超，最終仍要以市佔論成敗，但在這談方面，三星 2016 年晶圓代工市佔 7.9%，全球排第四，遙遙落後台積電的 50.6%。（日經新聞）
另外據三星預測，全球晶圓代工市場今年將創造 610 億美元的產值，較 2016 年成長 7.2%，明年更是上看 652 億美元。
（本文由 MoneyDJ新聞 授權轉載；首圖來源：Samsung）
>>>各家大廠對於投產三星還是會有忌諱，雖然獨立出來了，但是以韓國人的個性，難保不會有機密外洩發生，如果投給專業代工廠，沒
有利害關係，大廠都會投誰??? 答案就出來
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ebola01 wrote:
討論交流園地【定存...(恕刪)
终结台积电垄断地位 三星明年重新为iPhone代工芯片
http://www.cnbeta.com/articles/tech/632799.htm
据《韩国先驱报》北京时间7月18日报道，在2013年被台积电夺走iPhone芯片代工订单后，三星电子将于明年再次为苹果公司的新iPhone生产芯片。三星已在近期购买了极紫外光刻机专为iPhone生产7纳米移动处理器。极紫外光刻机是最先进的芯片制造设备。
消息称，三星负责芯片和其它零部件业务的联席CEO权五铉(Kwon Oh-hyun)为这笔交易的达成发挥了关键作用，他在上月造访了苹果总部。
“权五铉可能说服了苹果高管，要利用好双方在OLED屏幕上的密切合作关系，”行业消息称。三星目前是全球最大移动OLED屏幕制造商，市场份额高达95%，也是今年即将推出的新iPhone的独家OLED屏幕供应商。
三星一直是苹果的主要芯片代工商，直到2013年。那一年，台积电成为了iPhone芯片的独家代工商。通过比对手提前使用更为高效的7纳米工艺，台积电成功赢得了明年的iPhone代工订单。报道称，三星将承担一部分明年的iPhone芯片订单。
三星计划在不久后完成对新芯片制造机器的自主测试，然后寻求获得苹果在芯片生产上的最终批准。台积电现在是全球第一大芯片代工公司，份额为50.6%。
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