-Two to eight cores.
-Integrated DDR3 triple-channel memory controller.
-Individual 256 KB L2 memory caches for each core.
-8 MB L3 memory cache.
-New SSE 4.2 instruction set, with the addition of seven new instructions for string and text processing, collectively called “Application Target Accelerators”.
-Two-way simultaneous multi-threading (SMT).
-Enhancements on the microarchitecture (4-way dispatch unit).
-Enhancements on the prediction unit, with the addition of a second Branch Target Buffer (BTB).
-A second 512-entry Translation Look-aside Buffer (TLB).
-Improved virtualization performance.
-New QuickPath external bus (two links per CPU socket).
-45 nm manufacturing technology.
